1. Field of the Invention
This invention relates generally to a non-volatile integrated circuit memory. More particularly this invention relates to single polycrystalline silicon floating gate electrically erasable programmable read only memory (EEPROM) and flash electrically erasable programmable read only memory (flash memory).
2. Description of Related Art
In the semiconductor industry, generally, there are two important kinds of CMOS memories—“volatile” and “non-volatile”. The “volatile” memory, in which the stored data is not retained when its low-voltage VDD power supply is removed or shut down. The volatile memories include Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM).
The “non-volatile” memory (NVM), in which the stored data would not be corrupted and normally is retained for more than 20 years even after the power supply voltage source (VDD) is completely disconnected. Today, there are many different kinds of NVM memories aimed for different applications. For example, the most popular NVM today is NAND flash with a very small cell size of about 0.5 T cell size of 4λ2 (λ2 being the smallest area capable for a given semiconductor process) and is generally used to store huge blocks of data necessary for audio and video serial applications. The highest available memory density is up to 16 Gb and is currently made of 45 nm in 2008. The second largest revenue of NVM is NOR flash with one-transistor cell of about 10λ2 and is used to store the program code. Today, the highest available NOR memory density is about 2 Gb in the market place and is made of 70 nm in 2007. The third type of NVM is 2-transistor floating gate tunnel oxide (FLOTOX) EEPROM with cell size of about 80λ2. Currently, the density of EEPROM is around 1 Mb only and is used in byte-alterable application. Unlike NAND and NOR Flash Ram that only allows big-block data alterability, EEPROM can achieve the largest number of program/erase (P/E) cycles. In the current design, the EEPROM is capable of 1M P/E cycles when accomplished in units of bytes for small data change applications.
There are several disadvantages for NVM. The on-chip, high-voltage devices, charge-pump circuits, and the complicated double-polycrystalline silicon cell structure are required for the basic erase and program operations. Currently the above NVM cell devices are made of a complicated, double-polycrystalline silicon, high-voltage process.
There are several disadvantages for the double-polycrystalline NVM cells, described above. The required voltages for performing a program and erase operation are too high for devices that are fabricated using standard CMOS logic process. For example, the current 0.5 transistor per NAND cell structure requires +20V for Fowler-Nordheim tunneling program or erase operations. For a single transistor NOR flash cell, the channel-hot-electron program operation needs about +10V. However, the Fowler-Nordheim tunneling erase operation, requires both +10V and −10V. A current two-transistor EEPROM memory cell structure requires +15V for both Fowler-Nordheim tunneling program erase. As a consequence, the program and erase operations for the above described three NVM cells require an on-chip charge-pump circuit that provides the high-voltage levels that range from approximately 10V to approximately 20V. The peripheral devices of the NVM array thus require a high voltage breakdown for the operation. The high-voltage breakdown voltages are not compatible with the current process technology for the peripheral single-poly low-voltage logic devices. Having to implement the necessary process modifications to accomplish this high-voltage breakdown device requires that the manufacturing cost be increased.
“A New Single-Poly Flash Memory Cell with Low-Voltage and Low-Power Operations for Embedded Applications”, Chi, et al., The 5th Annual IEEE Device Research Conference Digest, June 1997, pp: 126-127, Posted ieeexlore.ieee.org: 2002-08-06 21:21:45.0, discusses a single-poly flash memory cell structure on triple-well CMOS technology and new program/erase schemes with operating voltage not exceeding ±Vcc. Conventional single-poly EPROM, although fully compatible with standard CMOS fabrication, suffers from high-voltage operation, slow programming, and incapability of electrical erase. The flash cell with the program/erase schemes permits low-voltage and low-power nonvolatile memory applications in CMOS mixed-signal circuits of system-on-a-chip.
U.S. Pat. No. 5,929,478 (Parris, et al.) describes a single level gate nonvolatile memory device that includes a floating gate FET and a capacitor fabricated in two P-wells formed in an N-epitaxial layer on a P-substrate. P+ sinkers and N-type buried layers provide isolation between the two P-wells. The NVM device is programmed or erased by biasing the FET and the capacitor to move charge carriers onto or away from a conductive layer which serves as a floating gate of the FET. Data is read from the NVM device by sensing a current flowing in the FET while applying a reading voltage to the capacitor.
U.S. Pat. Nos. 6,992,927 and 7,164,606 (Poplevine, et al.) provides a NVM array that includes four-transistor PMOS non-volatile memory (NVM) cells having commonly connected floating gates. Each of the four transistors execute distinct control, erase, write and read operations, thereby allowing each device to be individually selected and optimized for performing its respective operation.
U.S. Pat. No. 7,263,001 (Wang, et al.) teaches a non-volatile memory cell and array system. The array system includes rows and columns of NVM cells. Each of the NVM cells includes a floating gate, a programming element, and a logic storage element. During a programming or erase mode, the floating gate of each cell is charged to a predetermined level. At the beginning of a read mode, all storage elements are pre-charged to a high supply voltage level. Following the pre-charge, selected cells are read to determine stored bit values. A charge status of the floating gate of each cell determines whether the storage element is turned on and the pre-charge voltage is pulled down corresponding to a bit value.